Your question is Timing and Parasitics Analysis. Take a moment with it on the right.
Talk me through your thinking if you like. When you're confident, submit your answer and I'll grade it like a real screen (7/10 or better passes).
How do you approach timing analysis, transistor sizing, and parasitics in a hardware design? Treat timing slack, path delay, area, and power as measurable design metrics. Explain how you would use design data to identify critical paths, size devices, estimate parasitic effects, and validate improvements without creating regressions.