Your question is Clock Domain Crossing Design. Take a moment with it on the right.
Talk me through your thinking if you like. When you're confident, submit your answer and I'll grade it like a real screen (7/10 or better passes).
What is Clock Domain Crossing (CDC), and what design techniques do you use to prevent metastability?
Discuss how signals crossing between unrelated clock domains can violate setup and hold requirements, why metastability cannot be eliminated entirely, and how synchronization structures reduce its probability and system impact. Cover single-bit control signals, pulses, multi-bit data, asynchronous resets, and how CDC analysis verifies that crossings are safe.
Scope: RTL design for ASIC or FPGA systems, using SystemVerilog examples where useful.
