16-Bit Verilog Multiplexer | Dataford Interview Questions

Design a 16-bit multiplexer in Verilog.

Implement a synthesizable 2:1 multiplexer with 16-bit inputs a and b, a one-bit select signal sel, and a 16-bit output y. When sel is 0, y must equal a; when sel is 1, y must equal b. Provide the Verilog module and briefly explain the behavior. The Python function below models the same combinational logic for automated checks.

Constraints

a and b are 16-bit unsigned values from 0 through 65535
sel is either 0 or 1
The multiplexer is combinational and has no clock or reset
The output is a 16-bit value

Function Signature

def mux16(a, b, sel):

Your question is 16-Bit Verilog Multiplexer. Start with the requirements in the Question tab.

Run and submit as often as you like. When you're ready, talk me through your approach or go straight to the code.

Problem

Design a 16-bit multiplexer in Verilog.

Constraints

a and b are 16-bit unsigned values from 0 through 65535
sel is either 0 or 1
The multiplexer is combinational and has no clock or reset
The output is a 16-bit value

Function Signature

def mux16(a, b, sel):

Your question is 16-Bit Verilog Multiplexer. Start with the requirements in the Question tab.

Run and submit as often as you like. When you're ready, talk me through your approach or go straight to the code.