Synopsys Software Engineer interview experience

The questions consistently pulled from my experience with hardware design and verification-style thinking, including basics like Verilog/VHDL and how I would structure work using RTL coding and finite-state-machine models. I also got asked about system behaviors using items like testbench concepts and, in the same sweep, system verilog assertions.

As the rounds progressed, the focus sharpened around digital design implementation and verification detail. I ended up discussing digital design building blocks such as adders and logic optimization, and I was also prompted on verification or