Analog Devices Software Engineer interview experience

The discussion included typical setup and hold violations, along with metastability and how synchronizers handle it. It felt very specific to digital design timing behavior.

The conversation also covered SystemVerilog, and because of my background I got asked about formal verification. I liked that the questions were concrete; they weren’t framed as broad theory only, they were grounded in how those failure modes show up and get handled.

I didn’t receive an offer, but overall it felt like a fair, targeted technical screen that matched the topics the role seems to care about most.