What is a QA Engineer at Celestial AI?

As Generative AI continues to push the boundaries of modern computing, the fundamental architecture of data centers is shifting from systems-on-chip (SOCs) to expansive systems of chips. At Celestial AI, we are pioneering this transition with our Photonic Fabric™, a next-generation optical interconnect technology designed to shatter existing memory and bandwidth bottlenecks. As a QA Engineer (specifically operating as a Test Engineer - ATE & SLT), you are the critical gatekeeper ensuring that this groundbreaking hardware delivers the tenfold increase in performance and energy efficiency we promise to hyperscalers and tier-1 partners.

In this role, your impact is immediate and foundational. You are not just running routine quality checks; you are developing and optimizing the automated test strategies for highly complex semiconductor and optical components. Your work directly influences the yield, reliability, and market readiness of optical interface chiplets, interposers, and Optical Multi-chip Interconnect Bridges (OMIB). By ensuring our hardware functions flawlessly at bandwidths of tens of terabits per second with nanosecond latencies, you empower our customers to optimize their AI accelerators and GPUs for the next era of accelerated computing.

Expect a highly collaborative, fast-paced environment where hardware, firmware, and validation teams intersect. You will be tackling unprecedented engineering challenges at the boundary of digital, analog, and photonic testing. This role requires a blend of deep semiconductor test expertise, strong coding fundamentals, and the agility to thrive in an early-stage startup environment where your technical decisions shape the future of high-performance computing architecture.

Getting Ready for Your Interviews

Preparing for an interview at Celestial AI requires a strategic approach. We want to see how you bridge the gap between theoretical test methodologies and practical, high-yield production realities. Focus your preparation on the following key evaluation criteria:

Technical Depth in ATE & SLT We evaluate your hands-on mastery of Automated Test Equipment (ATE) and System-Level Testing (SLT). You should be able to discuss how you develop, debug, and optimize test programs for complex silicon, demonstrating familiarity with industry-standard platforms and test coverage methodologies.

Hardware Debugging & Failure Analysis Your interviewers will assess your ability to systematically isolate and resolve issues. Strong candidates will demonstrate how they analyze test data to identify root causes, improve yield, and collaborate with hardware and firmware teams to debug failures at both the component and system levels.

Scripting & Automation Proficiency Because efficiency is paramount, we look for your ability to automate data collection and test execution. You must be comfortable writing and debugging test scripts in Python, C/C++, or equivalent languages, proving that you can build scalable test infrastructure rather than relying solely on manual processes.

Adaptability & Cross-Functional Collaboration As an early-stage startup, Celestial AI values engineers who can navigate ambiguity and drive New Product Introduction (NPI). We evaluate your communication skills, your ability to define test requirements alongside design teams, and your readiness to learn emerging domains like integrated photonics testing.

Interview Process Overview

The interview process for the QA Engineer role is designed to rigorously evaluate both your hardware testing fundamentals and your problem-solving agility. You will typically begin with an initial recruiter screen to align on your background, compensation expectations, and overall fit for our startup environment. This is followed by a technical screen with a hiring manager or senior engineer, which will focus heavily on your past experience with ATE platforms, SLT, and your approach to semiconductor testing.

If you progress to the onsite or virtual panel stage, expect a series of deep-dive interviews. These sessions are highly interactive and will cover a mix of architecture discussions, live debugging scenarios, and behavioral questions. You will meet with cross-functional stakeholders—including hardware designers and firmware engineers—who will test your knowledge of communication protocols, boundary scans, and failure analysis. We highly value candidates who can back up their technical claims with data-driven examples of yield improvement and test optimization.

The timeline above outlines the typical progression from your initial application to the final offer stage. Use this visual to pace your preparation, ensuring you review core scripting concepts early on, while saving deep-dives into your past failure analysis case studies for the later panel rounds. Note that because we are a startup, the process can move quickly, and you may have the opportunity to speak directly with technical leadership.

Deep Dive into Evaluation Areas

To succeed, you must demonstrate a deep understanding of semiconductor testing and the specific challenges associated with high-speed, high-bandwidth interconnects. Below are the primary areas where you will be evaluated.

Automated Test Equipment (ATE) & System-Level Testing (SLT)

This is the core of the Test Engineer role. We need to know that you can translate product requirements into robust, high-yield test programs. Interviewers will look for your ability to write, debug, and optimize patterns on standard platforms.

Be ready to go over:

• Platform Experience – Your hands-on work with testers like Advantest, Teradyne, or LTX, including hardware setup and loadboard design considerations.
• Test Optimization – Techniques for reducing test time without compromising test coverage.
• SLT Methodologies – Bridging the gap between structural ATE tests and functional system-level environments.
• Advanced concepts (less common) – Multi-site testing strategies, thermal control during SLT, and handling massive parallel test data.

Example questions or scenarios:

• "Walk me through a time you successfully reduced test time on an ATE platform. What trade-offs did you consider?"
• "How do you ensure correlation between ATE results and SLT performance?"
• "Describe your process for developing a test program for a newly taped-out ASIC."

Failure Analysis & Yield Improvement

At Celestial AI, finding a defect is only the first step; understanding why it happened and how to prevent it is what drives our product forward. You will be evaluated on your systematic approach to root cause analysis.

Be ready to go over:

• Data Analysis – How you use statistical tools and data visualization to identify yield limiters.
• Debug Methodologies – Isolating faults between the device under test (DUT), the test hardware, or the test software.
• Cross-functional Debugging – Collaborating with design and firmware teams to implement corrective actions.
• Advanced concepts (less common) – Silicon characterization across process, voltage, and temperature (PVT) corners.

Example questions or scenarios:

• "You notice a sudden 5% yield drop on a mature production lot. Walk me through your debugging steps."
• "How do you differentiate between a silicon design flaw and a test program error?"
• "Tell me about a time you had to push back on a design team regarding testability requirements."

Communication Protocols & High-Speed Interfaces

Our Photonic Fabric™ interfaces with cutting-edge AI accelerators, meaning you must be fluent in the protocols that govern these interactions.

Be ready to go over:

• Low-Speed Control Protocols – Deep understanding of I2C, SPI, and UART.
• Test Interfaces – Practical application of JTAG (IEEE 1149.1) and boundary scan techniques.
• High-Speed Interfaces – Familiarity with PCIe and the fundamentals of high-speed signal integrity.
• Advanced concepts (less common) – RF testing basics, eye diagram analysis, and jitter tolerance.

Example questions or scenarios:

• "Explain how you would use JTAG boundary scan to verify the connectivity of a complex 2.5D packaged device."
• "What are the common failure modes you look for when testing a PCIe interface?"
• "How do you debug an I2C communication failure on a prototype board?"

Scripting & Test Automation

Manual testing cannot scale. We evaluate your ability to write clean, efficient code to automate data collection, control instruments, and parse complex test logs.

Be ready to go over:

• Python Proficiency – Using Python for instrument control, data parsing (Pandas/NumPy), and automation frameworks.
• C/C++ Skills – Writing low-level test scripts or firmware interactions.
• Data Infrastructure – Automating the pipeline from raw tester data to actionable yield reports.

Example questions or scenarios:

• "Write a Python script to parse a CSV log file and extract devices that failed a specific voltage threshold."
• "How do you manage version control and deployment for your test scripts across multiple ATE setups?"

Optics & Photonics Testing (Bonus/Preferred)

While not strictly required for all candidates, experience in this domain is a massive differentiator. Celestial AI's core technology relies on optical interconnects.

Be ready to go over:

• Optical Instrumentation – Using power meters, spectrum analyzers, and interferometers.
• Component Knowledge – Testing methodologies for lasers, modulators, and optical transceivers.
• Integration Challenges – Understanding the physical layer nuances of 2.5D packaging with optical components.

Key Responsibilities

As a QA Engineer / Test Engineer at Celestial AI, your day-to-day work will be highly dynamic, bridging the gap between pre-silicon design and post-silicon production. Your primary deliverable is the creation and continuous optimization of robust ATE and SLT test programs that ensure our semiconductor and optical components meet uncompromising quality standards. You will spend a significant portion of your time hands-on in the lab, debugging engineering samples and executing failure analysis to drive yield improvements.

Collaboration is central to this role. You will work in lockstep with hardware design, firmware, and validation teams to define test requirements during the New Product Introduction (NPI) phase. This means advocating for Design for Test (DFT) features early in the development cycle and ensuring that boundary scans and JTAG interfaces provide adequate coverage.

Furthermore, you will champion automation. Instead of manually pulling reports, you will develop Python and C/C++ scripts to streamline data collection, enabling the broader engineering team to visualize performance metrics and identify reliability trends rapidly. If you bring optics experience, you will also help pioneer testing methodologies for integrated photonics, directly shaping the validation of our Photonic Fabric™ ecosystem.

Role Requirements & Qualifications

To thrive as a QA Engineer at Celestial AI, you must possess a strong foundation in electrical engineering combined with practical, hands-on test experience in a high-tech manufacturing or R&D environment.

• Must-have technical skills – Deep expertise with ATE platforms (Advantest, Teradyne, LTX) and System-Level Testing (SLT). You must have a strong command of semiconductor testing methodologies, failure analysis, and yield optimization. Proficiency in Python or C/C++ for test scripting is non-negotiable. You also need a solid grasp of JTAG, boundary scans, and standard communication protocols like I2C, SPI, and PCIe.
• Experience level – A Bachelor’s or Master’s degree in Electrical Engineering coupled with 5+ years of relevant industry experience.
• Soft skills – Excellent problem-solving abilities, a proactive approach to debugging, and the communication skills necessary to collaborate effectively across hardware, firmware, and product teams in a fast-paced startup environment.
• Nice-to-have skills – Any experience with optics or photonics testing (lasers, transceivers) and optical instrumentation (power meters, interferometers) will heavily differentiate your application. Familiarity with high-speed signal integrity, RF testing, data visualization tools, and agile workflows (JIRA/Confluence) is also highly preferred.

Common Interview Questions

The questions below represent the technical depth and problem-solving scenarios you will encounter during your interviews. They are designed to test not just your theoretical knowledge, but your practical experience in a lab or production environment.

ATE & SLT Methodologies

These questions test your core competency in developing and optimizing test programs for semiconductor devices.

• Walk me through your process for bringing up a new test program on a Teradyne or Advantest platform.
• How do you balance test coverage with test time reduction in a high-volume production environment?
• Describe a time when SLT caught a defect that ATE missed. Why did that happen, and how did you resolve it?
• What are the key differences in your approach when testing digital logic versus analog interfaces?

Hardware Debug & Failure Analysis

Interviewers want to see your systematic approach to isolating faults and improving yield.

• You are seeing a consistent yield drop at a specific temperature corner. How do you investigate this?
• Explain how you use JTAG and boundary scans to debug an unresponsive device on a test board.
• Tell me about a time you had to perform root cause analysis on a complex hardware failure. Who did you collaborate with?
• How do you verify if a failure is caused by the DUT, the loadboard, or the tester itself?

Scripting & Automation

These questions evaluate your ability to build scalable test infrastructure.

• Write a Python function that reads a directory of test log files, extracts specific parametric data, and flags any values outside of a given tolerance.
• How do you structure your C++ or Python code to ensure it is reusable across different test engineering projects?
• Describe a tool or automation script you built that significantly improved your team's efficiency.

High-Speed Interfaces & Protocols

Given our focus on interconnect bandwidth, your knowledge of communication protocols is critical.

• Can you explain the initialization sequence of a PCIe link?
• How do you debug a scenario where an I2C bus is intermittently hanging?
• What considerations must be made when testing high-speed signal integrity on a heavily populated test board?

Frequently Asked Questions

Q: Do I need to be an expert in photonics to get this role? While experience with optics and photonics is a strong plus and highly preferred, it is not a strict requirement. If you are an exceptional ATE/SLT Test Engineer with strong fundamentals in semiconductor testing and automation, you are highly encouraged to apply. You will have the opportunity to learn the optics side on the job.

Q: What is the work environment like at Celestial AI? We are an early-stage startup, which means the environment is fast-paced, highly collaborative, and fluid. You will not be siloed into a single narrow task; you will have ownership over broad testing strategies and will work closely with brilliant minds across hardware and firmware disciplines.

Q: How much coding is actually required for this role? You will not be writing production software, but you must be highly proficient in scripting. Writing Python or C/C++ code for instrument control, test automation, and data analysis is a daily expectation.

Q: Will this role require me to be onsite? Yes. Given the hands-on nature of hardware debugging, ATE platform interaction, and lab-based testing, this role is based onsite at our Santa Clara, CA location.

Other General Tips

• Showcase your startup mindset: Celestial AI is moving fast. Emphasize moments in your career where you took initiative, operated with limited resources, or built test infrastructure from scratch.
• Be data-driven: When answering behavioral or failure analysis questions, use specific metrics. Talk about the percentage of yield improvement, the hours saved through automation, or the specific reduction in test time you achieved.
• Brush up on the physics: Even if you are testing at the system level, interviewers appreciate candidates who understand the underlying physics of the hardware, especially regarding thermal dynamics, signal integrity, and basic optics.
• Clarify ambiguity: During debugging scenarios, do not jump straight to a conclusion. Ask clarifying questions about the test setup, the environment, and the data available before proposing a root cause.

Summary & Next Steps

Joining Celestial AI as a QA Engineer / Test Engineer is an opportunity to be at the forefront of the AI hardware revolution. You will be directly responsible for validating the interconnect technologies that will define the next generation of data centers. By mastering ATE and SLT methodologies, demonstrating rigorous failure analysis, and showcasing your automation skills, you will prove that you are ready to tackle these complex challenges.

As you prepare, focus heavily on your ability to articulate your past debugging successes and your coding proficiency. Remember that your interviewers are looking for a colleague who can navigate the ambiguities of a startup while maintaining uncompromising standards for hardware reliability.

The compensation data above reflects the highly competitive nature of this role. At Celestial AI, the target base salary for this position ranges from $195,000 to$225,000, supplemented by a generous grant of early-stage equity and comprehensive benefits. Your final offer will be determined by the depth of your expertise, particularly if you bring premium skills like optics testing or advanced SLT architecture experience.

Approach your interviews with confidence. You have the foundational engineering skills required; now it is about demonstrating how you apply them to solve unprecedented hardware challenges. Best of luck with your preparation, and we look forward to seeing the innovative perspectives you bring to the team.