What is a Software Engineer at Celestial AI?

At Celestial AI, the role of a Software Engineer is inextricably linked to the physical reality of our hardware. We are not a traditional SaaS company; we are architecting the Photonic Fabric™, a technology that fundamentally breaks the "Memory Wall" in accelerated computing. As a Software Engineer here, you are likely working in domains such as Verification (UVM), CAD/EDA Automation, or SoC Integration. You are building the critical software infrastructure that validates, designs, and enables our optical interconnect technology to function at the tens of terabits per second required by next-generation AI.

Your work directly impacts how hyperscalers and data centers manage the massive bandwidth and latency demands of Generative AI. Whether you are developing Python scripts to automate complex analog/mixed-signal (AMS) design flows, writing SystemVerilog to verify our optical chiplets, or architecting the firmware that manages data traffic across our Optical Multi-chip Interconnect Bridges (OMIB), your code ensures that our hardware is manufacturable, reliable, and performant. You are the bridge between theoretical physics and mass-production silicon.

Common Interview Questions

These questions are based on real interview experiences from candidates who interviewed at this company. You can practice answering them interactively on Dataford to better prepare for your interview.

Getting Ready for Your Interviews

Preparing for an interview at Celestial AI requires a shift in mindset from pure software to hardware-software co-design. You will be evaluated not just on your coding ability, but on your understanding of the underlying engineering constraints.

Technical Proficiency & Domain Knowledge Interviews here are technically rigorous. Depending on your specific focus (Verification, CAD, or Design), you must demonstrate deep expertise in your toolset—whether that is SystemVerilog/UVM for verification, Python/Tcl/SKILL for EDA automation, or C++ for system modeling. You must show that you understand the semiconductor design lifecycle, from RTL to GDSII.

Problem-Solving in Constrained Environments We value engineers who can solve problems where the constraints are physical—thermal limits, signal integrity, and manufacturing yield. You will be asked to solve scenarios where "perfect" code is not enough; the solution must be efficient, scalable across massive clusters, and robust against the realities of silicon manufacturing.

Cross-Functional Collaboration Our technology relies on heterogeneous integration—combining photonics, electronics, and advanced packaging. You will be evaluated on your ability to communicate complex software concepts to analog designers, packaging engineers, and physicists. You must demonstrate that you can work effectively in a multidisciplinary environment where your software is a key enabler for other engineering teams.

Interview Process Overview

The interview process at Celestial AI is designed to assess technical depth and your ability to thrive in a fast-paced, Series B deep-tech startup environment. The process typically begins with a recruiter screen to align on your background and interest in the semiconductor/AI space. This is followed by a technical phone screen, usually with a hiring manager or a senior engineer, focusing on the specific methodologies relevant to the role (e.g., UVM concepts for verification, scripting for CAD).

If you pass the initial screens, you will move to the onsite stage (often conducted virtually or in-person at our Santa Clara or Irvine offices). This stage consists of a panel of interviews covering technical domain knowledge, problem-solving, and behavioral fit. You should expect deep-dive questions regarding your past projects, specifically how you handled technical roadblocks in chip design or verification. The team looks for hands-on experience; they want to know how you implemented a solution, not just the theory behind it.

This timeline reflects a standard engagement for engineering roles. Note that for specialized positions like UVM Verification or CAD Engineering, the "Technical Assessment" phase often involves detailed discussions on specific industry-standard tools (like Cadence Virtuoso or Synopsys tools) rather than generic algorithmic coding tests.

Deep Dive into Evaluation Areas

Based on the technical demands of our open roles, you must be prepared to demonstrate expertise in the following areas.

Verification Methodologies (UVM & SystemVerilog)

For verification-focused software roles, this is the core evaluation area. You must demonstrate mastery of Universal Verification Methodology (UVM). We do not just look for test execution; we look for the ability to architect robust testbenches from scratch.

Be ready to go over:

• Testbench Architecture – Building UVM environments, agents, drivers, monitors, and scoreboards.
• Constrained Random Verification – Writing effective constraints to hit corner cases in complex SoCs.
• Coverage Closure – Strategies for achieving 100% functional and code coverage.
• Advanced concepts – Register abstraction layer (RAL), TLM transactions, and UVM phases.

Example questions or scenarios:

• "How would you architect a UVM testbench for a high-speed SerDes interface?"
• "Describe a difficult bug you found using constrained random stimulus and how you debugged it."
• "How do you handle reuse of verification components from block level to SoC level?"

EDA Automation & Scripting

For CAD and infrastructure roles, your ability to automate design flows is critical. We rely heavily on Python, Tcl, and SKILL to glue together various tools in the ASIC flow.

Be ready to go over:

• Flow Automation – Automating tasks in tools like Cadence Virtuoso, Innovus, or PrimeTime.
• API Interaction – Interfacing with EDA tool APIs to extract data or drive simulations.
• Infrastructure Management – Managing compute resources (e.g., SLURM clusters) and license servers (FlexLM).
• Version Control – Managing design data with Git or IC Manage (gdpxl).

Example questions or scenarios:

• "Write a Python script to parse a large log file from a synthesis run and extract timing violations."
• "How would you automate the regression testing flow for a mixed-signal design?"
• "Explain how you would troubleshoot a license checkout failure in a distributed compute environment."

Semiconductor Design Flow Knowledge

Even if your role is purely software, you cannot treat the hardware as a black box. You need to understand the ASIC design flow to be effective.

Be ready to go over:

• RTL to GDSII – Understanding the steps: Synthesis, Floorplanning, Place & Route, CTS, and Signoff.
• Timing Analysis – Concepts of Setup/Hold time, Static Timing Analysis (STA), and timing closure.
• Physical Constraints – Understanding power, area, and thermal constraints in 2.5D/3D packaging.

Example questions or scenarios:

• "Explain the difference between a functional ECO and a timing ECO."
• "How does your code account for process variations in deep technology nodes (like 5nm)?"